features S4806CBI block diagram advanced product brief sts-48/stm-16 sonet/sdh framer and atm/pos mapper part number - S4806CBI product brief version 1.3 - april 2001 advanced information - the information contained in this document is about a product in its definition phase and is sub- ject to change without notice at any time. all features described herein are design goals.contact amcc for updates to this doc- ument and the latest product status. ohio amcc - confidential and proprietary 200 minuteman park, andover, ma 01810 ph: 978/623-0009 fax:978/623-0024 ? provides two sonet/sdh line interface modes of operation: single sts-48/stm-16 or quad sts-12/stm-4s. processes any valid combination of sonet/sdh sts-48c/ au-4-16c, sts-12c/au-4-4c, sts-3c/au-4, or sts-1/au-3 tributaries within an sts-48/stm-16 or sts-12/stm-4. terminates/generates sonet/sdh section, line, and optionally path overhead. sonet/sdh processing of all defined toh/poh bytes, compliant with bellcore gr-253 and ansi t1.105, and itu g.751, g.783, g.804. performs full-duplex mapping atm cells or packets for up to 48 payload tributaries. these tributaries can range in size from sts-48c/au-4-16c down to sts-1/au-3. supports full-duplex mapping of atm cells or packets into ds3 tributaries for atm over ds3 or packet over ds3 applica- tions. ds3 tributaries are then mapped into either sts-1s or stm-1s via au-3. atm mapping is compliant with the atm forum uni 3.1 speci- fication and itu-t i.432.1 and i.432.2. pos mapping is compliant with ietf rfc 2615. supports simultaneously atm, pos, tdm and direct-mapped traffic on a per tributary basis. provides a single 4x622 mhz telecom bus type system interface for add/drop of payload tributaries containing tdm traffic. this interface includes a 144x48 sts-1 level cross- connect for grooming of tdm tributaries. alternatively, this tdm port can be used to support protection- switching configurations between two ohio devices or two fiber optics modules. this 4x622mhz aps/tdm drop/add interface supports both synchronous and asynchronous operation. built-in 144x48 cross-connect capability in the tx direction. supports ring architectures such as add-drop, drop and continue, and hairpinning, as well as aps. provides a four bit 622 mhz line interface on the sonet/sdh side for sts-48/stm-16 applications; four serial 622 mhz signal for sts-12/stm-4 applications supports independent loop timing in quad sts-12/stm-4 line configuration provides a 100 mhz 32-bit flexbus-3 tm system interface; supports utopia level 3 mode for atm applications; for packet operation, can be provisionned either in extended utopia-3 mode or in oif spi-3 mode. programmable utopia/flexbus-3 tm addresses for multi-phy operation. loopback capability for sonet/sdh, atm and pos tributaries packaged in 624 pin cbga 0.18um cmos, 1.8v core and 2.5v i/o supply tx_sys_dat[31:0] poh mon toh drop toh mon rx frmr line side interface tx toh insert spe/vc gen rx_toh_clk_out[1:4] tx_toh_data_in[1:4] rx_toh_frm_out[1:4] d[15:0] addr[14:0] csn rdb(dsb) wrb(rwb) rdyb(dtackb) busmode intb microprocessor i/f jtag port gpio reg tdi tck tms trtsb gpio[15:0] tx_data_out_[3:0] tx_clk_out_[1:4] rx_data_in_[3:0] rx_clk_in_[1:4] tx_8k_clk rx_losext[1:4] rx_alarm_out[1:4] rstb aps_intb ts_en dxc x48 tdo tx_prty tx_soc/p tx_clk tx_enb tx_adr[5:0] tx_clav/pa[1:4] rx_sys_dat[31:0] rx_prty rx_soc/p rx_clk rx_enb rx_adr[5:0] rx_clav[1:4] tx_frm_out tx_tdm_data_out[1:4] rx_tdm_idata_n[1:4] utopia-3 or flexbus tm interface tx fifo x48 fifo x48 rx tx x48 rx sel tx_clk_out tx_lbyte[1:0] tx_eop tx_err rx_clk_out rx_lbyte[1:0] rx_eop rx_err tx_toh_clk_out[1:4] rx_toh_data_out[1:4] tx_toh_frm_out[1:4] frmr ptr proc hdlc at m hdlc atm ds3 fr ds3 fr x48 x48 prot toh gen tx_refclk_in[1:4] sys_async_frm_in ptr pm ds3 dmap map prot frmr sys_refclk_out[1:4] sys_refclk_in tx_tdm_clk_out[1:4] prot dxc ptr proc rx_tdm_clk_in[1:4] poh_drop_dat/clk//ctl poh_add_dat/clk//ctl stpa srpa proc rx_tdm_losext_in[1:4] rx_tdm_alarm_out[1:4]
amcc - confidential and proprietary 200 minuteman park, andover, ma 01810 ph: 978/623-0009 fax:978/623-0024 sts-48/stm-16 sonet/sdh framer and atm/pos mapper product brief version 1.3 - april 2001 S4806CBI: ohio advanced product brief overview and applications the s4806 - ohio is a highly-integrated sts-48/stm-16 so- net/sdh framer and pos/atm mapper ic. the line interface can process either a single sts-48/stm-16 or four sts-12/stm-4 signals carrying a mix of atm, packet or tdm traffic. the s4806 integrates a sts-1 level cross-connect that allows to drop traffic through a dedicated expansion tdm port. alternatively, the tdm drop port can be used as a second sonet/sdh-compliant line interface to support aps between two ohio devices or two fiber optics modules. the s4806 also performs full path overhead (poh) generation and monitoring as well as full-duplex mapping of packets, cells or directly mapped traffic into tributaries ranging from ds3 over sts-1/au-3 to sts-48c. up to 48 tributaries can be processed simultaneously. for packets or cell transfers on the system bus, the flexbus- 3 tm system interface supports multiple configurations, including utopia 3 and oif spi-3 modes. the high level of integration, versatility and depth of channeliza- tion of the s4806 - ohio make it a perfect fit for aggregation edge equipment as well as multi-service switches. sonet processing the s4806 implements sonet/sdh processing functions for sts-48/stm-16 or four sts-12/stm-4 data streams. it can support any combination of sts-48c/au-4-16c, sts-12c/au-4- 4c, sts-3c/au-4, and/or sts-1/au-3 signals within an sts-48/ stm-16, or any combination of sts-12c/au-4-4c, sts-3c/au- 4 or sts-1/au-3 signals within the sts-12/stm-4 data streams. the s4806 provides full section, line and path over- head processing of all defined toh/poh bytes, including fram- ing, scrambling/descrambling, alarm signal (ais) insertion/ detection, remote failure indication insertion/detection (rdi/ rei), and bit-interleaved parity (bip) processing. the ohio provides programmable signal fail (sf) and signal degrade (sd) thresholds for each line and path interface. the s4806 is sonet and sdh standards compliant with bellcore gr-253 and gr-499, ansi t1.105 and itu g.707 and g.783. atm processing the s4806 can be configured for atm processing on a per trib- utary basis. the s4806 can terminate up to 48 data tributaries carrying atm cells , with data rates anywhere from sts-48c/ au-4-16c down to sts-1/au-3. cells received from or sent to the system interface can be either 52 or 56 bytes long transmit atm processor in the transmit direction, the s4806 ? s atm processor will per- form all necessary cell encapsulation including optional hec generation, cell payload scrambling (x 43 +1), and idle cell inser- tion to adapt the cell rate to the spe or ds3 frame rate. when mapping into ds3 frames, cells are either nibble-aligned with ds3 multiframes or encapsulted in plcp frames before being mapped into the ds3 frame. receive atm processor when receiving data from the line side, it performs cell delinea- tion, hec checking, descrambling, and receive cell rate adapta- tion by discarding idle cells. the s4806 is atm standards compliant with atm forum uni 3.1, itu-t i.432.1 and i.432.2. pos hdlc processing the s4806 can be configured for pos hdlc processing on a per tributary basis. the s4806 can terminate up to 48 data trib- utaries carrying packet traffic, with data rates anywhere from sts-48c/au-4-16c down to sts-1/au-3. byte-stuffed hdlc processor (pos mode) in packet over sonet mode, the s4806 ? s transmit hdlc pro- cessor will provide the insertion of hdlc framed packets into the synchronous payload envelope. it optionally inserts provi- sionned address and control fields and generates a 16 or 32 bit fcs. it also performs transparency processing, optional pay- load scrambling (x 43 +1) and inter-frame time fill. the receive hdlc processor provides for the delineation of hdlc frames, de-scrambling (if enabled), transparency removal and fcs error checking. the hdlc address and con- trol fields are optionally checked and can be either dropped or passed-through the system interface. the s4806 also provides a robust set of counters and status/control registers for perfor- mance montoring via the microprocessor. bit-stuffed hdlc processing (ds3 mode) for packet over ds3, the s4806 supports bit-stuffed hdlc mapping and demapping of packets into ds3 frames. transpar- ency processing is performed by adding a ? 0 ? after each sequence of five contiguous ? 1 ? and packets are then mapped bit-by-bit into the ds3 frame. for each frame, a fcs is com- puted, appended to the frame and transparency processed. during inter-frame fill time, the flag sequence is normally trans- mitted but the s4806 can optionally be provisioned to transmit 15 or more mark idle bits as required by some circuit-switched links. the receive bit-stuffed hdlc processor performs removal of inter-frame flags, transparency processing and fcs checking. the s4806 is pos/hdlc standards compliant with ietf rfc 1662/2615. additionally, the s4806 hdlc processor support ip and ethernet mapping over sonet/sdh using link access procedure -sdh (laps) as proposed by itu x.85 and x.86. direct map mode the s4806 provides with the ability to directly map the traffic received from the flexbus-3 tm system interface into the syn- chronous payload envelope (sonet/sdh tributaries) or ds3 frames (ds3 over sts-1/au-3 mode). in this mode, the atm and hdlc processors are by-passed and other protocols like ethernet can be mapped into sonet/sdh.
amcc - confidential and proprietary 200 minuteman park, andover, ma 01810 ph: 978/623-0009 fax:978/623-0024 sts-48/stm-16 sonet/sdh framer and atm/pos mapper product brief version 1.3 - april 2001 S4806CBI: ohio advanced product brief ds3 processing the s4806 can be configured to support ds3 mapping/demap- ping of atm, hdlc or directly-mapped payloads on a per tribu- tary basis. the s4806 supports the c-bit parity and m23 ds3 frame formats. ds3 frame generation (transmit) in the transmit direction, the s4806 maps the data received from the atm or hdlc processor into the payload of a ds3 frame. it also generates ds3 overhead bits and, for channels operating in c-bit mode, inserts the terminal to terminal data link information. additionally, the ohio can be provisionned to generate idle or ais signals on any active ds3 channel. the ds3 frames are subsequently mapped into sonet sts-1 spe or in sdh vc3 virtual container. ds3 framing and demapping (receive) in the rx direction, the s4806 frames the ds3 signals and monitors the signal for errors, alarms or idle conditions detec- tion. in c-bit mode, it extracts the data link channels and makes it available to the user through an external interface. the data payload is demapped and passed through the atm, hdlc or direct map mode processors. for testing purposes, the s4806 includes a pseudo random bit sequence generator (tx) and monitor (rx) and any one ds3 can be replaced by a prbs sequence. tdm/circuit drops in addition to the flexbus tm system interface, the s4806 also provides a single telecom-type interface to allow for add/drop of tdm tributaries. this tdm interface can operate as either a 4- bit wide sts-48/stm-16 signal, or as 4xsts-12/stm-4 sonet/sdh signals, both operating at 622.08 mhz. the signal format adheres to the sonet/sdh frame structure, with valid a1a2, b1 and h1h2h3 pointer bytes. for backplane applications, the tdm port ? s high speed serial link mode provides clock recovery for the 622mhz signals as long as a low speed (78mhz) reference clock that is frequency synchronous to the data stream is supplied to the device. the tdm port can interface directly to the amcc s1204 orinoco device, or the s2509. the s1204 orinoco will interface with the sts-12/stm-4 tdm ports of the s4806, and provide insertion/extraction of ds3, e3 or clear channel sts-1/stm-0 tributaries to/from these tdm add/drop signals. the s2509 pro- vides the capability to serialize a 4-bit wide sts-48 signal into a single 2.5 gb/s serial backplane signal. redundancy features the 4x622 mb/s tdm ports can also be used as aps input and output interfaces to convey signals between two s4806 devices configured for aps operation. this configuration supports 1+1 and 1:1 protection in linear, upsr and blsr configurations. the tdm interface provides fully compliant sonet/sdh trans- mit and receive toh monitoring/generation for both 4-bit wide sts-48/stm-16 and 4xsts-12/stm-4 modes of operation. this enables the use of the tdm port as a redundant line inter- face, allowing a single ohio device to support linear 1+1 and 1:1 protection. cross-connect the s4806 provides integrated cross-connection functionality, to support all types of ring configurations, including hairpinning, drop-add, drop-and-continue, and broadcast/multicast. a 144x48 sts-1 level cross-connect is placed in the transmit direction of the s4806. the inputs to the cross-connect block come from the 48 transmit atm/hdlc processing blocks, the receive data path, and the input tdm/aps port. additionally, the s4806 provides a 144x48 sts-1 level cross- connect capability in front of the tdm/aps output port, to allow for grooming of the tdm/aps interface signals. the inputs to this cross-connect come from the receive data path, the receive tdm port and the spe / vc generator. line-side interface for sts-48/stm-16 operation, the s4806 supports a 4-bit par- allel line-side interface which operates at 622.08 mhz. in this mode, the device is connected to the s3455 mux/demux and clock recovery device. (see figure below.) for sts-12/stm-4 operation, the s4806 supports four serial line interfaces which operate at 622.08 mhz. in this application, the device is con- nected to four s3024 clock recovery devices. system interface the s4806 provides a flexbus-3 tm system interface to allow the transfer of atm cells or packet data between the s4806 and a link layer device. for atm cell transfer, the flexbus-3 tm inter- face operates as a 100 mhz 32 bit utopia level 3 interface. the s4806 supports multi-phy operation for up to 48 tributar- ies. it also provides multiple tx/rx_clav signals for multi- plexed polling operation. for packet/direct data transfer, the flexbus-3 tm interface extends the utopia framework to accomodate the variable length nature of packet traffic. in this mode, the s4806 also sup- ports multi-phy operation for up to 48 tributaries with multiple tx/rx_pa signals for multiplexed polling operation. alterna- tively, it can be configured to operate in spi-3 mode as defined by the optical internetworking forum (oif). the flexbus-3 tm interface also has extensions to support direct map mode oper- ation. microprocessor interface the user of the s4806 can select between an 8-bit asynchro- nous or a 16-bit synchronous microprocessor interface for device control and monitoring. the interface supports both intel and motorola type microprocessors, and is capable of operating in either an interrupt driven or polled-mode configurations.
amcc - confidential and proprietary 200 minuteman park, andover, ma 01810 ph: 978/623-0009 fax:978/623-0024 sts-48/stm-16 sonet/sdh framer and atm/pos mapper product brief version 1.3 - april 2001 S4806CBI: ohio advanced product brief applications termination of mixed tdm and data traffic in multi- service switches dense traffic aggregation in atm switches and ip routers multi-service metropolitan access nodes sonet/sdh multiplexers, including 2 fiber blsr architectures. mapping of ethernet traffic into sonet/sdh using laps tx_data_out[3:0] sys_refclk_in[1] rx_clk_in[1] rx_data_in[3:0] p/s & s/p sonet xcvr with clk recovery serrxd sertxd microprocessor control control amcc s3455 reference clock fiber optic transceiver sonet sdh interface rx_losext S4806CBI ohio addr data 8/16 tx_clk[1] tx_sys_dat[31:0] rx_clk[1] rx_sys_dat[31:0] toh insertion and extraction atm layer f l e x b u prot ds3/e3/sts-1 clear channel rx_tdm_data_in_[1:4] tx_tdm_data_out[1:4] tx_tdm_clk_out[1:4] ds3/e3/sts-1 line card channelized atm and/or packet data typical application s1204 line side sts-48/stm-16 orinoco 1 4 packet proc or s
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